In the past, wafer production is made on two-dimensional (2D) space. With more wafer complexity, increasing lateral area on two-dimensional space is unable to make the Moore's Law continuingly effective. Therefore, using stacked way to integrate different wafers is developed recently. The three-dimensional integrated circuit (3DIC) is the integration mode of wafers with three-dimensional stacking overlay. The characteristics of 3DIC include connecting circuits functions made on different substrate wafers. As shown in FIG. 1, a technology uses a suitable manufacturing process to produce each of a thinned wafer 110, a thinned wafer 120, and a base wafer 130, then uses a Through-Silicon Via (TSV) technology to perform the stacked integration to shorten the metal length and the metal line resistance, thereby reducing the silicon area that may satisfy digital electronic requirements of small volume, high integration, low power consumption, low cost, and compact developed trend.
The TSV packaging technology integrates wafer stacks through a vertical conduction to make wafers electrically connected. However, good electrical interconnection should avoid producing a stacking overlay error. The stacking overlay error also affects wafer yield. When a plurality of wafers are stacked together, and measuring a stacking overlay error is very important. Three-dimensional wafer stacking methods may be divided into face-to-face, face-to-back, and back-to-back methods. Wherein the face-to face method uses inter-die via or uses micro bump for intra-die interconnection instead of using the TSV technology. The face-to-face method may only be used for two layers in the three-dimensional wafer stacking, while the remaining layers of this stacking uses the face-to-back method.
Usually, the 3D wafer stacking produces some marks used for measuring the stacking overlay. When wafers are stacked together, it may generally use bright-field optical microscope of near infrared (NIR) wavelength as a measurement tool of overlay mark. FIG. 2 shows an exemplary schematic view of an overlay mark, wherein a measurement system 200 through a prism 222 produces a structure of two light spots on a lower layer overlay mark 220 and an upper layer overlay mark 240 of a wafer, and the lower layer overlay mark 220 and the upper layer overlay make 240 are placed adjacently, and are all with a periodic grating structure. Using this overlay mark, FIG. 3A shows an exemplary schematic view for an illumination light path of a measurement system. As shown in FIG. 3A, when an incident light 334 enters into a prism, such as a Wollaston prism 320, the incident light is separated into an extraordinary ray (E-ray) 334a and an ordinary ray (O-ray) 334b; and these two rays are respectively incident to the light spot 326 of the lower layer overlay mark 220 and the light spot 328 of the upper layer overlay mark 240 via an objective lens 360.
Using the characteristics of the grating structure, the reflected light after the incident light incident on the overlay mark is divided into the +1 order and the −1 order. Wherein the reflected light of the lower layer overlay mark and the upper layer overlay mark of the +1 order is received by the detector to obtain the signal S+1, while the reflected light of the lower layer overlay mark and the upper layer overlay mark of the −1 order is received by the detector to obtain the signal S−1. Then, the Wollaston prism 320 moves along the y direction, the variation of the S+1 signal and the S−1 signal are shown in FIG. 3B. As shown in FIG. 3B, there is a shift between the S+1 signal and the S−1 signal, whereby the stacking overlay error of the lower layer overlay mark 220 and the upper layer overlay mark 240 of the wafers may be obtained through the shift.
Because there is a silicon wafer of a certain thickness between the upper layer overlay mark and the lower layer overlay mark of the wafer, using bright-field optical microscopy measurements may be unable to focus on the upper layer overlay mark and the lower layer overlay mark simultaneously. Therefore, separately focusing on the upper layer overlay mark and the lower layer overlay mark is required. After measuring the upper layer overlay mark and the lower layer overlay mark, the overlay error value is analyzed by software. When the focusing position of the upper layer overlay mark moves to the focusing position of the lower layer overlay mark, the introducing horizontal movement may cause a measurement error, and also increase the required measurement time. Therefore, when multiple wafers are stacked together, the accumulation of the stacking overlay error would seriously affect the wafer yield.
Therefore, it is an important issue to design a technology for measuring a stacking overlay error, without respective focusing on the upper layer overlay mark and the lower layer overlay mark when measuring, while just focusing on the lower layer overlay mark to obtain an overlay error value between the upper layer wafer and the lower layer wafer.